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C8051F380/1/2/3/4/5/6/7/C
USB Register Definition 21.18. E0CNT: USB0 Endpoint0 Data Count
Bit
7
6
5
4
3
2
1
0
Name
E0CNT[6:0]
Type
R
R
Reset
0
0
0
0
0
0
0
0
USB Register Address = 0x16
Bit Name
Function
7
Unused
Read = 0b. Write = don’t care.
6:0 E0CNT[6:0] Endpoint 0 Data Count.
This 7-bit number indicates the number of received data bytes in the Endpoint 0
FIFO. This number is only valid while bit OPRDY is a 1.
21.11. Configuring Endpoints1-3
Endpoints1-3 are configured and controlled through their own sets of the following control/status registers:
IN registers EINCSRL and EINCSRH, and OUT registers EOUTCSRL and EOUTCSRH. Only one set of
endpoint control/status registers is mapped into the USB register address space at a time, defined by the
contents of the INDEX register (USB Register Definition 21.4).
Endpoints1-3 can be configured as IN, OUT, or both IN/OUT (Split Mode) as described in Section 21.5.1.
The endpoint mode (Split/Normal) is selected via the SPLIT bit in register EINCSRH.
When SPLIT = 1, the corresponding endpoint FIFO is split, and both IN and OUT pipes are available.
When SPLIT = 0, the corresponding endpoint functions as either IN or OUT; the endpoint direction is
selected by the DIRSEL bit in register EINCSRH.
Endpoints1-3 can be disabled individually by the corresponding bits in the ENABLE register. When an End-
point is disabled, it will not respond to bus traffic or stall the bus. All Endpoints are enabled by default.
196
Rev. 1.4
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